The present invention relates to a method and device for measuring the capacitance of a capacitive component.
More specifically, the present invention relates to a method and device for accurately determining the capacitance of a capacitive component varying as a function of a physical quantity, such as the amount of liquid in a vessel; to which the following description refers purely by way of example.
As is known, some electronic devices currently used to determine the amount of liquid in a vessel or the pressing of a key employ a capacitive component varying in capacitance as a function of the quantity to be determined; and a measuring device connected to the capacitive component to measure its capacitance and provide a quantitative indication of the physical quantity causing the variation in capacitance.
Some measuring devices used for the above purposes are of digital circuit architecture, wherein a multivibrator stage is connected to the capacitive component to oscillate and generate a train of pulses frequency-related to the capacitance of the capacitive component. The multivibrator stage is also connected to a counter stage, which counts the pulses generated by the multivibrator stage and supplies an interrupt signal when the pulse count, as of a start instant in which a reset signal is received, reaches a predetermined count threshold.
The reset signal and interrupt signal are generated/received by a microprocessor with an internal clock for measuring the time interval between the instant the reset signal is generated and the instant the interrupt signal is received, and on the basis of which the capacitance of the capacitive component is determined.
By way of a non-limiting example, FIG. 1 shows a measuring device 1 of digital architecture as described above, and for measuring the capacitance of a capacitive component 4 defined, for example, by a capacitor. The capacitor comprises a first plate, and a second plate polarized to a ground potential VGND; and the first and second plate respectively define a measuring electrode 4a and a reference electrode 4b of measuring device 1, which are typically located in a vessel to determine a liquid level.
More specifically, measuring device 1 substantially comprises a microprocessor processing unit 2, which generates a reset signal R synchronized with the instant an internal clock 2a is activated, and which receives an interrupt signal I to stop the clock; and a pulse generating circuit 3, in turn comprising a multivibrator stage 5 and a counter stage 6.
More specifically, multivibrator stage 5 has a terminal 5a receiving reset signal R; a terminal 5b connected to measuring electrode 4a; a terminal 5c connected to reference electrode 4b; and an output 5d which generates a switching signal B defined by a train of rectangular pulses D frequency-related to the capacitance of capacitive component 4, as shown in FIG. 2.
More specifically, multivibrator stage 5 is typically defined by a Schmitt trigger, and counter stage 6 has a terminal 6a which receives reset signal R to start the count of pulses D; a terminal 6b which receives the train of pulses D; and a terminal 6c which generates interrupt signal I when the number of pulses D reaches a predetermined trigger threshold Th.
With reference to FIG. 2, the capacitance of capacitor 4 is measured by measuring device 1 at predetermined time intervals TI, each started by the microprocessor generating reset signal R.
During each time interval TI, microprocessor 2 activates the clock and, at the same time, supplies reset signal R to multivibrator stage 5 and counter stage 6.
More specifically, reset signal R is received as a trigger pulse by multivibrator stage 5, which switches from a rest condition to an oscillating condition (point P in FIG. 2) in which multivibrator stage 5 generates pulses D with a frequency proportional to the capacitance of capacitive component 4.
Reset signal R also starts the count of pulses D by counter stage 6.
As long as the pulse D count is below predetermined trigger threshold Th, interrupt signal I switches to a first, e.g. high, logic level. Conversely, when the pulse D count equals predetermined trigger threshold Th (point E in FIG. 2), interrupt signal I switches to a second—in this case, low—logic level to stop the pulse count. At this point, microprocessor 2 determines the time interval TA between the start and end of the pulse D count, and accordingly calculates the capacitance value.